TM datasheet. MediaDeckGX Datasheet LK datasheet cn-O SRT Datasheet V1.
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TM datasheet. MediaDeckGX Datasheet LK datasheet cn-O SRT Datasheet V1. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications.
The digitally controlled oscillator DCO allows wake-up from low-power modes to active mode in less than 1? For configuration details see Table 1. Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Package drawings, thermal data, and symbolization are available at www. NAME P1. This is due to the oscillator output driver connection to this pad after reset. Submit Documentation Feedback 7 Copyright? NAME P3. The device protection fuse is connected to TEST. Connection to VSS is recommended. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 3 shows examples of the three types of instruction formats; Table 4 shows the address modes.
Table 3. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software:? Active mode AM — All clocks are active? The vector contains the bit address of the appropriate interrupt handler instruction sequence.
Table 5. Multiple source flags non -maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Interrupt flags are located in the module. A zero 0h disables the erasure of the flash if an invalid password is supplied. Special function register bits not allocated to a functional purpose are not physically present in the device.
Simple software access is provided with this arrangement. Legend rw: rw-0,1: rw- 0,1 : Bit can be read and written. Bit can be read and written.
It is reset or set by PUC. It is reset or set by POR. SFR bit is not present in device. Table 6. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Flag set on oscillator fault. Power-On Reset interrupt flag. Set on VCC power-up. External reset interrupt flag. Reset on VCC power-up. Table 9. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:?
Flash memory has n segments of main memory and four segments of information memory A to D of 64 bytes each. Each segment in main memory is bytes in size. Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also called information memory. Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required. Oscillator and System Clock The clock system is supported by the basic clock module that includes support for a Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator DCO.
The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1? The basic clock module provides the following clock signals:? Main DCO Characteristics? Table Any combination of input, output, and interrupt condition port P1 and port P2 only is possible.
Edge-selectable interrupt input capability for all bits of port P1 and port P2 if available. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.
Not all packages support the USCI functionality. The module implements a bit SAR core, sample select control, reference generator, and data transfer controller DTC for automatic conversion result handling, allowing ADC samples to be converted and stored without any CPU intervention.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. Higher temperature may be applied during board soldering according to the current JEDEC J-STD specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Modules might have a different maximum input clock specification.
See the specification of the respective module in this data sheet. Flash program or erase operations require a minimum VCC of 2. Figure 1. Safe Operating Area Copyright? Outputs do not source or sink any current. The internal and external load capacitance is chosen to closely match the required 9 pF.
Supply Voltage? V f DCO? DCO Frequency? MHz Figure 2. Current for brownout included. Typical Characteristics, Low-Power Mode Supply Currents over recommended ranges of supply voltage and operating free-air temperature unless otherwise noted 3. The leakage of the digital port pins is measured individually. The output is connected to the center tap of the divider. Typical Low-Level Output Current?
Low-Level Output Voltage? V Figure 6. Typical High-Level Output Current? High-Level Output Voltage? V VOH?
MSP430 LaunchPad Tutorial - Part 4 - UART Transmission
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Datasheet Texas Instruments MSP430G2553
This tutorial is written for very beginners and no hardware is required except the MSP board and a computer. The main purpose of this board it to upload code from the computer to the MCU and read serial data from the MCU for debugging purpose. Hence in this series of tutorials, we will be using the MSPG to explore all the functionalities of this Development kit. You can power board through the mini USB jack and once you do it, you should notice the LEDs red and green at the bottom left corner of your board glowing alternatively.
MSP430 General Purpose Input Output (GPIO)