CHIPSCOPE ILA PDF

This document introduces the Xilinx ChipScope Analyzer. ChipScope is a set of tools made by Xilinx that allows you to easily probe the internal signals of your design inside an FPGA, much as you would do with a logic analyzer. For example, while your design is running on the FPGA, you can trigger when certain events take place and view any of your design's internal signals. The sample memory of the analyzer is limited by the memory resources of the FPGA.

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If you are new to FPGAs, one aspect of the development flow you may not have considered is how you will go about debugging your design once it has been loaded into the FPGA. One of the tools we would have employed would be a logic analyzer. We might also specify certain trigger conditions upon which we desired the tool to commence storing data for subsequent display and analysis.

Then we would run the system and try to work out what the heck was happening. Logic analyzers are, of course, still employed today. This means that you may have to keep on rebuilding your design to access the signals of interest and route them out to the test header. In some cases, the physical construction of the unit in question means that test headers are of use only at the board level and not during system integration.

Indeed, I am working on one such project at the time of this writing. And one further problem is that, inevitability, the logic analyzer you are using will also be required by one or more other project teams, which means you all have to agree on how you will allocate the analyzer resources. One solution to this problem — a solution that has seen great advances over the last few years — has been the development of in-chip logic analyzers for use with FPGAs.

As with their physical counterparts, these virtual logic analyzers — like ChipScope from Xilinx, Identify RTL Debugger from Synopsys, Reveal from Lattice Semiconductor, and SignalTap from Altera — can be set up so that they will only start collecting data after certain trigger conditions have been met.

Using virtual logic analyzers may remove the need for test headers. Sadly, however, in many cases they do not remove the need to rebuild the code. One big advantage of these in-chip logic analyzers is that they offer the ability to capture the values on wide internal busses and store these values in internal RAM.

The big downside with this approach comes in designs that are already utilizing most of the devices programmable resources, because this will limit any logic analyzer implementations.

This is where you will connect the signals you wish to analyze. Having configured the target device, you can then connect to the target over JTAG using the ChipScope Analyzer tool and trigger on the waveform of interest as illustrated in the screenshot below.

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